A known technique for obtaining extremely fine frequency resolution in a phase lock loop (PLL) is to use a sigma delta modulator that modifies the value of N in a 1/N divider in the feedback loop of the frequency synthesizer. While the phase lock loop is in lock, the value of N is modified between two or more values, by use of a sequence of integer values that are typically low integer values (e.g., 0's and 1's). The sequence of integer values are coupled to the 1/N divider and an output of the 1/N divider is coupled to a phase-frequency detector. The sequence of integer values causes noise in the PLL that appears as modulation noise in the output of the PLL. An advantage of using a sigma delta modulator is that the noise is noise shaped such that its spectral content is concentrated at high frequencies. A low-pass response of the PLL attenuates the high frequency noise such that it does not significantly modulate the output of the PLL.
It has been experimentally determined that the transfer function for a PLL that uses a sigma delta modulator in this fashion must be very linear to avoid undesirable sequence value dependent responses that degrade the noise shaping properties of the sigma delta modulator. The portion of the PLL that most typically introduces such non-linearities and the resultant degradation is the phase-frequency detector, which typically is a charge pump detector.
Two types of charge pump detectors have been used in the past. Although they have both been successfully employed, both of them have undesirable characteristics that are increasingly important in modern, very low power and high frequency devices, such as pagers and cellular phones. The first type is a tri-state charge pump phase-frequency detector. In this type of phase-frequency detector, a pump up switched current source and pump down switched current sink are coupled together forming a charge pump output. When an output of the 1/N divider lags a reference signal, the pump up current source is activated, and when the output of the 1/N divider leads the reference signal, the pump down current source is activated. When the PLL is in phase lock, either the source or sink is turned on during each cycle for a very brief time. This tri-state charge pump has an advantage of very low average current drain, but the operation of the tri-state charge pump degrades the noise shaping of the sigma delta modulator due to gain and transient characteristic differences between the current source and sink that introduce a non-linear performance. It is very difficult in practice to match the gain differences and transient characteristics of the source and sink.
The second type of phase-frequency detector is a dual state phase frequency detector, in which a pump up constant current source is on continuously and a pump down current sink having twice the value of the pump up constant current source is turned on when the output of the 1/N divider leads the reference signal. This results in a 50/50 duty cycle. Switching only the pump down sink results in a very linear charge pump output characteristic. Although this approach substantially reduces noise due to non-linearity, it generates undesirable noise from the constant current source and the switched current sink, which are active a large portion of the time. The high duty cycle is particularly a problem in CMOS devices which are desirable for their low cost but which inherently have high flicker noise. This has resulted in the use of expensive bipolar or BiCMOS processes in high performance applications.
Thus, what is needed is a linear phase-frequency detector that reduces the coupling of device noise into the PLL output.